|The DG535 Digital Delay and Pulse Generator provides four precisely-timed logic transitions or two independent pulse outputs. The delay resolution on all channels is 5 ps, and the channel-to-channel jitter is typically 50 ps. Front-panel BNC outputs deliver TTL, ECL, NIM or variable level (-3 to +4 V) pulses into 50 Ω or high impedance loads. The high accuracy, low jitter, and wide delay range make the DG535 ideal for laser timing systems, automated testing, and precision pulse applications.|
DG535 Digital Delay/Pulse Generator
The DG535 Digital Delay and Pulse Generator provides four precisely-timed logic transitions or two independent pulse outputs. The delay resolution on all channels is 5 ps, and the channel-to-channel jitter is typically 50 ps. Front-panel BNC outputs deliver TTL, ECL, NIM or variable level (-3 to +4 V) pulses into 50 Ω or high impedance loads. The high accuracy, low jitter, and wide delay range make the DG535 ideal for laser timing systems, automated testing, and precision pulse applications.
There are four delay output channels: A, B, C and D. The logic transitions of these outputs can be delayed from an internal or external trigger by up to 1000 seconds in 5 ps increments. The T0 pulse, which marks the beginning of a timing cycle, is generated by the trigger signal. The insertion delay between an external trigger and the T0 pulse is about 85 ns.
Delays for each channel may be "linked" to T0 or any of the other delay channels. For instance, you can specify the delays of the four channels as:
A = T0 + 0.00125000
B = A + 0.00000005
C = T0 + 0.10000000
D = C + 0.00100000
In this case, when the A delay is changed, the B output will move with it. This is useful, for instance, when A and B specify a pulse and you want the pulse width to remain constant as the delay of the pulse is changed. Regardless of how the delay is specified, each delay output will stay asserted until 800 ns after all delays have timed out. The delays will then become unasserted, and the unit will be ready to begin a new timing cycle.
In addition to the four delay outputs, there are four pulse output channels: AB, -AB, CD and -CD. The leading edge of the AB pulse coincides with the leading edge of the earlier of A or B, and the trailing edge of AB coincides with the leading edge of the later of B or A. For instance, in the previous example, a 50 ns pulse would appear at the AB output and a 1 ms pulse at CD. Pulses as short as 4 ns (FWHM) can be generated in this manner. The complementary outputs (-AB and -CD) provide a pulse with identical timing and inverted amplitude.
Output Amplitude Control
Each delay and pulse output has an independently adjustable offset and amplitude which can be set between -3 V and 4 V with 10 mV resolution. The maximum transition for each output is limited to 4 V. In addition, you can also separately select 50 Ω or high impedance termination for each output. Preset levels, corresponding to standard logic families, can also be selected. TTL, NIM and ECL levels can all be selected with a single key press.
The DG535 can be triggered internally from 1 mHz to 1 MHz with four-digit frequency resolution. External, single-shot and burst mode triggers are also supported. For power control applications, the DG535 can be synchronized to the AC line. An optional trigger inhibit input allows you to enable or disable triggering with a TTL input signal.
±32 Volt Outputs
For applications requiring higher voltages, a rear-panel high voltage (±32 V) option is available. This option provides five rear-panel BNCs which output 1 µs pulses at the transitiontimes of the front-panel T0, A, B, C and D outputs. The high voltage option does not affect the function or the timing of the front-panel outputs. The amplitude of the rear-panel outputs is approximately 8× the corresponding front-panel output, and the outputs are designed to drive 50 Ω loads. Since these outputs can only drive an average current of 0.8 mA, charging and discharging the cable capacitance may bethe most important current limiting factor to consider when using them (assuming a high impedance load). In this case, the average current is: I = 2Vtf/Z, where V is the pulse step size, t is the length of the cable in time (5 ns per meter for RG-58), f is the pulse repetition rate, and Z is the cable's characteristic impedance (50 Ω for RG-58).
Internal or External Timebase
Both internal and external references may be used as the timebase for the DG535. The internal timebase can be either the standard 25 ppm crystal oscillator timebase, or the optional 1 ppm Temperature Compensated Crystal Oscillator (TCXO). The internal timebase is available as a 1 Vpp square wave on a rear-panel BNC. This output is capable of driving a 50 Ω load and can be used to provide a master timebase to other delay generators. Any external 10.0 MHz reference signal with a 1 Vpp amplitude can also be used as an external timebase.
Fast Rise / Fall Time Modules
Fast Rise and Fall Time Modules
External in-line modules are available to reduce the rise or fall time of the DG535 outputs to 100 ps. These modules use step recovery diodes to speed up the rise time (option SRD1) or the fall time (option O4B). A bias tee (option O4C) allows these modules to be used with the optional rear-panel outputs to produce steps up to 15 V. For step amplitudes of less than 2.0 V, the fast transition time units should be attached directly to the front panel of the DG535.
Easy to Use, Easy to Program
All instrument functions can be accessed through a simple, intuitive,menu-based interface. Delays can be entered with the numeric keypad in either fixed-point or exponential notation, or by using the cursor keys to select and change individual digits. The backlit 20-character LCD display makes it easy to view delay settings in all lighting conditions.
The DG535 comes standard with a GPIB (IEEE-488) interface. All instrument functions can be queried and set via the interface. You can even display the characters the DG535 has received over the interface on the front-panel LCD display. This can be valuable when debugging programs which send commands to the instrument.
DG535 Timing Diagram
A timing cycle is initiated by an internal or external trigger. T0 is asserted approximately 85 ns after an external trigger. Outputs A, B, C and D are asserted relative to T0 after their programmed delays. All of the outputs return low about 800 ns after the longest delay. The pulse outputs, AB and CD, go high for the time interval between their corresponding delay channels.
|tcycle||>1 µs + longest delay|
|tBUSY||<800 ns + longest delay|
|tA,B,C,D||0 to 999.999 999 999 995 s|